1. Field of the Invention
The present invention relates to a semiconductor device fabrication method and an apparatus that applies particles to selected areas of a substrate to be processed using a stencil mask.
2. Description of the Related Art
According to a semiconductor device fabrication method using a stencil mask, an entire circuit pattern of a semiconductor device or part thereof is formed on a stencil mask as a pattern of through-holes. Next, particles are irradiated onto selected areas in a substrate to be processed via circuit pattern through-holes formed on the mask, dealing a circuit pattern on the substrate to be processed.
According to some semiconductor device fabrication methods using the stencil mask, the size of the circuit pattern formed on a mask may be equal to that of a circuit pattern formed on a substrate to be processed. For example, those methods include ion implantation using a stencil mask, low energy electron beam proximity lithography, X-ray lithography or related methods. The particles include ions, electrons and photons.
According to these fabrication methods that allow formation of a circuit pattern on a substrate to be processed that equal in size to a circuit pattern formed on a stencil mask (hereafter, called a ‘proximity projection process’), when there is a difference in size between a design size of a circuit pattern using a stencil mask and the actual circuit size of the circuit pattern formed on the stencil mask during a fabrication process, use of a stencil mask in processing a substrate to be processed always creates a misalignment.
In addition, the proximity projection process and a process using a photo mask, which is obtained by enlarging a circuit pattern so as to carry out image reduction exposure such as photolithography (hereafter, called an ‘image reduction process’), may be used together for semiconductor device fabrication. Differences in reduction ratio from the photo mask for a circuit pattern to a substrate to be processed occurs during the image reduction process. The circuit pattern on a substrate to be processed is obtained by enlarging or reducing a designed circuit pattern. When subjecting the substrate to be processed to proximity projection, since a circuit pattern formed on the substrate to be processed is equal to a designed circuit pattern, misalignment occurs between the circuit pattern formed in the underlying layer of the substrate to be processed and an additionally formed circuit pattern.
Consideration of this misalignment as well as the size of a designed circuit pattern when designing a circuit may achieve a desired performance of a semiconductor device; however, the size of the semiconductor device is enlarged.